Course Details

Course Information
SemesterCourse Unit CodeCourse Unit TitleT+P+LCreditNumber of ECTS CreditsLast Updated Date
3EE213DIGITAL DESIGN LAB1+2+02214.08.2025

 
Course Details
Language of Instruction English
Level of Course Unit Bachelor's Degree
Department / Program COMPUTER ENGINEERING
Type of Program Formal Education
Type of Course Unit Compulsory
Course Delivery Method Face To Face
Objectives of the Course The objective of this course is to familiarize the student with fundamental principles of digital design. It provides coverage of classical hardware design for both combinational and sequential logic circuits. In the combinational logic circuits, logic gates, minimization techniques, arithmetic circuits are explained. In the sequential circuits: flip-flops, synthesis of sequential circuits, and case studies, including counters, registers, and random access memories are presented.
Course Content HDL Introduction

Block design with IP

Combinational logic design

Sequential logic design

Finite state machines
Course Methods and Techniques Laboratory experiments will be conducted in groups of two students.

For most experiments, the Xilinx Vivado Design Suite Webpack software will be used. This software is available free of charge at www.xilinx.com/products/design-tools/vivado.html and can be installed on both Windows and Linux operating systems. To run the software, students must register on the Xilinx website. Each student is required to install the software on their personal computer.

Unless otherwise specified, the Basys™ 3 Artix-7 FPGA board will be used in the lab sessions. The boards will be provided during the lab but must not be removed from the laboratory.

A minimum of 70% attendance is required to pass the lab component of the course. (This attendance rule applies specifically to the lab and may differ from the main Digital Design course.)

All group members share equal responsibility for completing the assigned lab tasks. Each student is expected to answer questions posed by the lab assistants individually.

If an experiment is accompanied by a tutorial, the relevant materials (video or documents) will be uploaded to Canvas one week prior to the lab session. Students are expected to check the platform regularly and come to the lab prepared, having reviewed the materials in advance.
Prerequisites and co-requisities None
Course Coordinator None
Name of Lecturers Asist Prof.Dr. ABDULKADİR KÖSE abdulkadir.kose@agu.edu.tr
Assistants None
Work Placement(s) No

Recommended or Required Reading
Resources - M. M. Mano, C. R. Kime, T. Martin, “Logic and Computer Design Fundamentals,” 5th Ed., Pearson, 2015
T. L. Floyd, “Digital Fundamentals,” 11th Ed., Pearson, 2015
Course Notes Laboratory Experiment Sheets and Tutorial videos

Course Category
Engineering Design %100

Planned Learning Activities and Teaching Methods
Activities are given in detail in the section of "Assessment Methods and Criteria" and "Workload Calculation"

Assessment Methods and Criteria
In-Term Studies Quantity Percentage
Laboratuar 15 % 70
Final examination 1 % 30
Total
16
% 100

 
ECTS Allocated Based on Student Workload
Activities Quantity Duration Total Work Load
Deney 15 2 30
Simülasyon 15 1 15
Yazılım Deneyimi 15 1 15
Final Sınavı 1 2 2
Total Work Load   Number of ECTS Credits 2 62

 
Course Learning Outcomes: Upon the successful completion of this course, students will be able to:
NoLearning Outcomes
1 Apply knowledge in analyzing and designing digital logic circuits using HDL.
2 Gain hands-on experience in block design with Intellectual Property (IP) components, integrating pre-designed functional blocks into larger digital systems using HDL.
3 Develop skills for implementing digital circuits and systems on FPGA boards covering both combinational and sequential logic design.

 
Weekly Detailed Course Contents
Veri yok

 
Contribution of Learning Outcomes to Programme Outcomes
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
C1 5 3 5 4 3 3 2 2 1 1 5 3 5 5 2
C2 4 3 4 5 3 3 2 2 1 1 5 2 4 5 2
C3 4 3 5 5 3 2 2 2 1 1 5 2 4 5 2

  Contribution: 1: Very Slight 2:Slight 3:Moderate 4:Significant 5:Very Significant

  
  https://sis.agu.edu.tr/oibs/bologna/progCourseDetails.aspx?curCourse=78310&lang=en